This invention pertains to printed circuits, and more particularly to a process for manufacturing a multilayer printed circuit substrate using high temperature thermoplastic materials.
There are a number of thermoplastic materials that can be molded or otherwise formed into shapes of printed circuit substrates. To be a suitable material for a printed circuit substrate, however, the material should be able to withstand the temperatures that result from soldering. When ordinary tin/lead solders are used, the substrate must be able to withstand temperatures in the region of 200.degree.-230.degree. C. If low temperature solders are used, however, the substrate needs to withstand slightly lower temperatures in the region of 170.degree.-200.degree. C. Accordingly, the term "high temperature thermoplastic" will be used in the specification to indicate thermoplastic materials that have a heat deflection temperature of 170.degree. C. or greater, as determined by the American Society of Testing and Materials (ASTM) standard test No. D648. Such materials include poletherimide (PEI), polysulfone, polyethersulfone, polyarylsulfone, polyarylate, polybutyleneterephthalate, polyetheretherketone and blended combinations thereof.
Generally speaking, there are three processes for applying printed circuit patterns to thermoplastic substrates; specifically, foil bonding, electroless plating and the vacuum deposition process which is described in a co-pending application entitled "High Temperature Thermoplastic Substrate Having A Vacuum Deposited Solderable Electrical Circuit Pattern And Method Of Manufacture". These processes can be used to manufacture single and double sided thermoplastic printed circuit substrates, but additional process steps are necessary to manufacture a multilayer substrate.
A prior art multilayer thermoplastic printed circuit substrate is illustrated in FIG. 1. Referring to this figure, to manufacture the multilayer substrate 100, two double sided thermoplastic printed circuit substrate layers 102 and 104 are adhesively bonded together by an intermediate layer of epoxy 106. Each of the double sided substrate layers 102 and 104 has upper and lower printed circuit patterns 102A and B, and 104A and B respectively, which are electroless plated onto the individual substrate layers. Printed circuit pattern 102A is plated completely through a hole 102C in the upper substrate and onto the lower surface of a protuberance 102D that surrounds the hole. Similarly, printed circuit pattern 104B is plated completely through a hole 104C in the lower substrate and onto the inner surface of an indentation 104B. When the substrate layers 102 and 104 are joined, protuberence 102D mates with indentation 104D, thereby forming a conductive through-hole 102C/104C which electrically joins printed circuit patterns 102A and 104B.
Described below is a different and improved method of manufacturing a multilayer thermoplastic printed circuit substrate.